L1 Cache with Dynamic Coverage of an External Memory

This article is about a study of ways to organize a cache of the first level to minimize access to an external memory. The article briefly describes the logic of the direct mapping cache and the multi-associative cache, as well as an example in which the use of both types of the caches significantly increases the load on an external memory. As an alternative, the organization of a cache with a programmable external memory coverage is proposed. It’s a similar in logic of a work with a direct mapping cache, but with an ability to dynamically change a structure of an address. The resulting organization can significantly reduce a load on an external memory in some situations, while maintaining full backward compatibility with a direct-display cache memory. To evaluate the effectiveness theoretical calculations were used on the number of accesses to external memory in the case of using the direct mapping cache and cache with programmable external memory coverage.