Assessment of ITCs on Dual Metal Strip Based Charge plasma TFET: Analog to Linearity analysis

With this present research work, authors stated that a novel CP TFET in which drain, and gate engineering are integrated with two distinct metal strips in the oxide area. The use of hetero dielectric in the gate region gives improved performance. This research aims to find out how both positive (electron donor, P-ITC) and negative (hole acceptor, N-ITC) interface trap charges affect Dual Metal Strip Dual Metal Gate Hetero-dielectric Drain engineering-based CP TFET (DMS DG DE CP TFET) as well as the conventional device's (CP TFET) performance. So, an extensive study has been carried out for different parameters such as
$\mathbf{I}_{\text{ds}}\text{-}\mathbf{V}_{\text{gs}}$
characteristics along with transconductance (gm), intrinsic delay, gate-to-drain and source capacitances (
$\mathrm{C}_{\text{gd}}$
and
$\mathrm{C}_{\text{gs}}$
), fT (cutoff frequency), and transconductance frequency product (TFP). In addition, a comprehensive investigation was carried out to explain the dependency of linearity metrics such as
$\mathrm{g}_{\mathrm{m}2}$
, VIP2,
$\mathbf{IMD}_{3},\ \text{gm}_{3}, \mathbf{VIP}_{3}$
, and
$\mathbf{IIP}_{3}$
on the ITCs variation.