Analysis of the Proposed Dynamic XNOR Circuit using Dual Keeper with Twist-Connected Transistors

In this paper, two circuits have been introduced, namely, XNOR using single keeper with Twist-NOT (T-NOT) gate and XNOR using dual keeper with TNOT gate, to achieve high speed for improvement in delay, power, and power-delay product (PDP). A dynamic Complementary Metal Oxide Semiconductor (CMOS) circuit with a low PDP and dual keeper transistor is proposed. It is a combination of two techniques to obtain a small-scale swing at the dynamic node of the pull-down network that is discharged in the pre-charge condition
$\mathrm{v}_{\text{dd}}$
to ground and charge to
$\mathrm{v}_{\text{dd}}$
in the evaluation condition. The delay can be minimized by reducing the loop gain connected with the feedback loop; this can be done by splitting the keeper transistor into two keeper transistors maintaining the strength, without any charge in noise margin, area, and nominal performance. The proposed circuit reduces power, overall delay, and PDP. This proposed circuit has been performed in the virtuoso platform using the Cadence tool with 90 nm CMOS-technology using gpdk library at various power sources 0.9V, 1.0V, and 1.2V.