Design of 32nm Phase locked loop for 5G Technology

In this paper, low power and low area phase locked loop has been proposed which can be used for 5G applications. The design of proposed circuit is implemented in Microwind using 32 nm CMOS technology. PLL is used to align an output signal of oscillator to that of a reference signal. For generating a 5GHz output frequency, a voltage supply of 2.0V with an input frequency of 10 GHz is supplied. The power consumption of the phase locked loop is 0.277 mW and covers a surface area of
$\boldsymbol{25.4 \mu \mathrm{m}^{2}}$
.