Implementation of parallel multiplier based on Booth computing method using FPGA

Several architectures are available for multipliers in the literature. A parallel multiplier can perform faster multiplication than a serial multiplier. The design of proposed multiplier is carried out by a sequence of steps: partial products are generated in first stage, recoded partial products are added until two rows are obtained, and in the last stage the corresponding rows are added to get the end result. In this paper, the multiplication is implemented with modified Booth Encoding technique. For generating a partial product a novel scheme for booth encoding scheme (BNS) is proposed in the paper for the performance improvement of existing schemes. During the multiplication process, addition of partial products is performed using a partial product reduction tree (OPPT) method. The OPPT will be constructed using Three-Dimensional-reduction-Method (3DRM). At the last stage the addition is carried out by using multi-stage conditional adder (MSCA) (MSCA)algorithm. The design is implemented using Verilog HDL on Xilinx Vivado software and synthesized on Spartan-6 FPGA board.