Signal Integrity Analysis of Neuronal Spike Signal in 3-D Packaging

Prompted by the continual advancements in artificial intelligence, the neuromorphic chip based on a spiking neural network (SNN) has attracted considerable attention because of its beneficial architecture of memory computing integration. Unlike traditional artificial neural networks, SNNs process information based on discrete-time spikes. This unique spike signal tends to bring an entire new series of signal integrity (SI) problems in three-dimensional (3-D) packaging. In this article, the resistance–inductance–capacitance–conductance (RLGC) equivalent circuit of through-silicon vias (TSV) and redistribution layer (RDL) structure was modeled in 3-D packaging. Furthermore, the spike SI issues, such as reflection, delay, and loss of spike signals, were also analyzed in 3-D packaging. The results illustrated that the corners between RDL and TSV in 3-D packaging could lead to reflections on the spike signals, resulting in distorted waveforms and increased signal loss. The time delay of the spike signal is only related to the electrical characteristics of the transmission link itself and not to the input signal. In addition, the SI of the spike signal was simulated with possible internal voids as well as the open and short defects in the 3-D packaging. The findings also demonstrated that both open and short defects distort the spike signal's waveform, whereas internal voids almost do not affect the signal. This article presents the first systematic analysis of numerous SI issues of spike signals in 3-D packaging while providing a specific reference for designing neuromorphic chips.