SEU Prediction for Very Integrated Circuits based on Advanced Physical Considerations

SET compact modeling for SEU prediction is faced to new challenges for advanced technological nodes. Some works have already addressed these challenges, proposing modeling approach for new relevant physical aspects like bipolar amplification, 3D charge deposit morphology, and bipolar amplification. Very recently, we have developed a fully compact SET model for very integrated technologies taking these effects into account, suitable for SPICE simulations. In this paper, we propose to couple this SET compact model with MUSCA SEP3 soft errors simulation plateform, in order to address soft error risk assessment for very integrated technologies. SBU/MCU predictions are performed in FDSOI based SRAM memories after TCAD calibration of our SET compact model. The purpose is to show how bipolar amplification, 3D charge deposit morphology, and SET/circuit coupling are able to influence simulated SBU/MCU cross sections values.