Design and Implementation of 4-bit and 8-bit KSA in 18nm FinFET Technology

The addition operation is required by any digital, analogue, or control system. The speed and accuracy with which the digital system operates is dependent on the functioning of adders. Adders are utilised in a variety of logical and arithmetic procedures. The goal of VLSI system design research is to improve the performance of digital systems, hence there is a strong incentive to examine and analyse adder architectures. The purpose here is to understand the family of faster adders available, such as the Ripple Carry Adder, Carry Look Ahead Adder, Carry Select Adder, and so on. This paper is about the Kogge Stone Adder in the 18nm FinFET model's technology node. It has a high PDP because it operates at a faster rate than its competitors. The adder is designed and built for bit lengths of 4 and 8, with random input data simulations used to evaluate its operations. Criteria such as power, performance, area, gate count, and PDP are used to construct a comparison. Every block used to construct the adder is inspected, and the results are graphically shown. In order to properly examine the parameters, the acquired data is tabulated.