Temperature Analysis of a Novel 5nm Stacked Oxide Top Bottom Gated Junctionless FinFET for improved switching and efficiency

Temperature Analysis of a Novel Stacked Oxide Top Bottom Gated Junctionless Fin-shaped Field Effect Transistor (TBG JL FinFET) is described in this research paper. This examinations reveals the alteration of performance parameters with temperature for the Novel 5nm Stacked Oxide TBG JL FinFET. The Temperature Analysis is done on Silvaco TCAD tools for the Novel Stacked Oxide Top-Bottom Gated Junctionless FinFET and compared with the Conventional Junctionless FinFET structure. The device shows enhanced output performance at 200K while having less electric field near drain end concurrently, thus reducing the Short Channel Effects (SCEs) by a greater extent. The results from device simulation reveal that the Novel Stacked Oxide Top-Bottom Gated Junctionless FinFET has better analog performance over varied temperature range and lowers the Short Channel Effects (SCEs) a cut above the Conventional Junctionless FinFET.