Hardware Implementation of Moving Object Detection using Adaptive Coefficient in Performing Background Subtraction Algorithm

Moving object detection is an essential process in many surveillance systems, autonomous navigation systems, and computer vision applications. A hardware architecture for the motion detection process based on the background subtraction operation and with the introduction of an adaptive background update coefficient is proposed. The architecture is implemented on a Kintex 7 FPGA device. Its operating frequency is 250 MHz for 360*640 video frame size and average processing time for each frame is 2.304 ms with 130 fps processing rate and its power consumption is 140 mW. The architecture achieves high speed performance with relatively low resource utilization.