Design of Low-Voltage Low-Power CMOS Second Generation Current Conveyor by using the Genetic Algorithm

This article mainly aims at reducing the power consumption and optimizing the performances of CMOS positive second-generation Current Conveyor (CCII+) by using a biological-inspired algorithm named Genetic Algorithm (GA). The optimized CCII+ reduces the total power consumption by 25.5%. The optimal configuration of CCII+ is used as a building block of a relaxation oscillator. SPICE simulation results are presented to validate the good reached performances.