A Design Methodology of MOS Current Mode Logic Pre-Scaler for ZigBee Applications

Current-mode logic (CML) pre-scalers are extensively used in radio-frequency transceivers and phase-locked loops for its wide division range. This paper presents a methodology for the design of metal-oxide-semiconductor CML (MCML) pre-scaler compliant with the ZigBee standard. A hand calculation based general analysis is presented in this work. A delay element has been introduced in the pre-scaler architecture and the theoretical foundations of the method have been explained. The methodology has been applied to the divide-by-3 pre-scaler.