Series-Resonance BiCMOS VCO with Phase Noise of -138dBc/Hz at 1MHz Offset from 10GHz and -190dBc/Hz FoM

The phase noise of oscillators limits the modulation Error Vector Magnitude (EVM) in wireless communications and the SNR in high-speed data converters. The issue is particularly critical in the wireless infrastructure for 5G and beyond, where base stations and backhaul transceivers need extremely low phase noise to support wide bandwidth and spectrally efficient modulation schemes at high carrier frequency. Given the supply voltage, the phase noise in LC oscillators is reduced by scaling down the inductance and increasing power consumption. However, the Q degradation with too-small inductors sets a lower bound on phase noise [1], [2]. To overcome this limit, oscillators evolved from a single-core to multicore topologies, where N oscillators are coupled to scale down phase noise by 10log(N). This concept was exploited with two cores [1] and then extended to four [2]–[4] and eight cores [5], giving ideally the phase-noise reduction of 3, 6, and 9dB, respectively. Nevertheless, mismatches between oscillators impair phase noise and penalize the figure of merit (FoM) [3]. Moreover, with the number of cores that grows exponentially, the extension of the approach for further phase-noise reduction is not practical.