Chisel-based Implementation of High-performance Pipelined Priority Queue Generator

Priority queues are widely used in Domain-specific accelerators, such as task scheduling in graph neural network accelerators, and packet routing in network switches. This paper presents an implementation of a high-performance priority queue generator based on the agile hardware design language Chisel. The priority queue generator can generate hardware implementations of priority queues of any data type with any depth. In addition, this priority queue generator can support 1. Completing the Enqueue and Dequeue operations with a constant two clock cycles; 2. Generating RTL code without redundant hardware description. In this article, we have described in detail the 1. Chisel-based priority queue hardware generator implementation and related data structure; 2. Testbench used to measure the performance of the generator; 3. Power and area overhead under 32nm technology node.