Improving Soft Error Reliability of FPGA-based Deep Neural Networks with Reduced Approximate TMR

Deep Neural Networks (DNN) are recently used in different fields such as autonomous driving, cancer detection, and also space explorations. A certain level of reliability of DNN are indeed needed to be applied in these fields. More recently, FPGA devices have become a target platform for DNN applications due to their high flexibility and computational power. Unfortunately, the SRAM-based FPGAs are considered to be susceptible to soft errors which can lead to errors in execution. Triple Modular Redundancy (TMR) is one of the effective mitigation techniques for masking SEUs for FPGA but causes an increase in power consumption and area overhead. In this study, we evaluate the reliability of MNIST DNN implemented in Xilinx SRAM-based FPGA. Through fault injection simulation, we identified the most vulnerable parts of the design that SEU can generate errors. We improved the SEU reliability of DNN with our proposed hardening strategy named reduced approximate TMR. SEU reliability was enhanced by applying reduced approximate TMR to the most sensitive layers of MNIST DNN, achieving 40% improvement in reliability while recourses utilization and power consumption were increased by 8% and 4%, respectively.