High-Performance CVD MoS2 Transistors with Self-Aligned Top-Gate and Bi Contact

We fabricated high-performance MoS
2
FETs featuring large-area CVD MoS
2
channel, self-aligned top-gate, and semi-metallic Bi Ohmic contact. For the first time, semi-metallic Bi was used in the top-gate 2D FET as source/drain contacts to achieve zero Schottky barrier and reduce contact resistance (
$R_{\mathrm{C}}$
). The devices showed
$I_{\text{ON}}$
of
$680\ \mu \mathrm{A}/\mu \mathrm{m}$
at 60 nm gate length (
$L_{\mathrm{g}}$
) and
$R_{\mathrm{C}}$
of
$280\ \Omega\cdot\mu \mathrm{m}$
, which are the best reported values among top-gate 2D FETs. It is predicted that, by scaling down the gate length to sub-10 nm technology nodes, our proposed top-gate MoS
2
FET technology will meet the requirement of the IRDS 2028 targets of logic transistors.