Hotspot Mitigation through Multi-Row Thermal-aware Re-Placement of Logic Cells based on High-Level Synthesis Scheduling

Place and route tools do only consider area and timing when placing a synthesized netlist. This can lead to a placement with high-density power regions, which in turn lead to hotspots. This work presents a method to re-place logic cells locally, within the hotspot, to reduce the peak temperatures, leveraging the fact that placed rows contain fillers between cells. One key contribution of this work is that it optimizes all of the rows simultaneously instead of traditional methods that do a row-based optimization. This is accomplished by formulating the cell placement problem as a system of difference constraints (SDC). SDC constraint were mainly proposed to solve the operation scheduling in High-Level Synthesis. In this work we propose two methods that apply this global optimization problem for the thermal-aware re-placement of logic gates. Experimental results show that our proposed methods lead to better results than optimizing every row independently leading to average peak temperature reduction of 5.2°C and 9.5°C with minimum delay overhead.