Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration

We propose a fast interposer bus router that observes the complex design rules of silicon interposer layers and optimizes the signal integrity. By escaping highly integrated physical layers (PHYs) of chiplets and sharing the same bus topology, our router compactly interconnects thousands of bump I/Os within a short timeframe. In addition, we secure the maximum wire pitch and guard the signal wires to optimize the signal integrity in high bandwidth. Compared with the results of a commercial EDA tool, our router is about five times faster and the results are verified to transmit signal in a target data rate with 30% improved eye width and 35% improved eye height for industrial designs. Our router can provide practical routing results for the upcoming 2.5D ICs that have more chiplets and require higher bandwidth than the existing chips.