VLSI Implementation of a High Speed and Area efficient N-bit Digital CMOS Comparator

This paper deals with a comparator with N bits which is efficient in terms of area and operates at high speed with power dissipation as low as possible. Area and power necessities can be scaled down by this proposed digital comparator. Among all the arithmetic operations comparison is the most basic. This operation directs if one number is less than, greater than, or equals to the other number. In our proposed model comparison is carried out bit wise up to least significant from most significant bit , when bits are equal only then comparison forgoes ,which is called as parallel prefix tree structure is exercised. This proposed methodology of comparator structure comprises of two independent modules .Comparison evaluation unit (CEU) and final unit (FU) named first and second units respectively. For implementing tree structure results obtained from systematic structure of repeated logic cells is validated. By depending on the outcomes of CEU, FU module authenticates the result. The presence of structured VLSI methodology in the mooted architecture grants the area derivation through analytical method relating transistors count and entire total delay can be seen in terms of operand bit width. By making use of 0.18 micron CMOS technology at 1 GHz spectre simulations have been performed. Using this proposed design, power consumption reduced by 77.76% and operating speed had increased by 31.92% when compared with existing model.