Verilog-HDL Based Implementation of Sum of Absolute Difference Architecture using Adder Compressors

Sum of Absolute Difference (SAD) is a popular method for video encoding, but it is very tedious and complex to calculate. The partial SAD value obtained from the absolute difference of two video blocks is added with the help of the adder tree in the originally proposed design. Later, a high-speed adder compressor was proposed to replace the adder tree for better performance. This paper describes the design of the high performance of SAD architecture using adder compressors instead of an adder tree, using Verilog - Hardware Descriptive Language with different combinations for the recombination line. The results obtained from the synthesis suggest that the SAD architecture is effective with Kogge-Stone adders (KSA) when compared to the other combinations. The development of the design is done on Xilinx’s Vivado 2018.3.