Design of a 14-bit Hybrid DAC for High Resolution Applications in SAR ADCs

A 14-bit differential Digital-to-Analog Converter (DAC) designed for the establishment in high-resolution Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC) is presented in this paper. The schematic design comprises of two single-ended DACs connected in parallel, with each DAC consisting of a 10-bit Resistor DAC (RDAC) and a 4-bit Capacitor DAC (CDAC) that constitute the hybrid architecture. The differential circuit is capable of producing the 14-bit digital-to-analog conversions at an input voltage of 3.3V across all process corners and temperatures with a conversion frequency of 2.5 MS/s. Detailed transient simulations at the schematic level specify that the circuit attains the 14-bit conversion with a maximum Differential Non-Linearity (DNL) of −0.0737, thereby inducing substantial linearity and minimal mismatch between the circuit components. The finalized schematic circuit designed using 0.18μm Complementary Metal-Oxide-Semiconductor (CMOS) process acquires the 14-bit conversion across all input codes, thus depicting the high resolution potency of the proposed DAC.