FPGA-Based Obfuscated Delay PUF for Security Enhancement Against ML-Attack

Arbiter-PUF is a promising candidate to provide security in resource-constrained Internet of Things (IoT) devices. However, Arbiter-PUF is vulnerable to modeling assaults. A promising technique that has been proposed in the past, known as a random challenge permutation technique, has advantages of low area overhead and resilience against ML-attack. However, the performance of this technique was only evaluated at the simulation level. Therefore, in this study, we implement an Arbiter-PUF with random challenge permutation technique on the Digilent Nexys-4 Artix-7 field-programmable gate array (FPGA) board. We prove that the susceptibility of conventional Arbiter-PUF against machine learning (ML) attacks reduce from ≈98% to ≈44% by implementing this technique. In addition, we also prove that the implementation of the random challenge permutation technique in FPGA introduced no area overhead in terms of the number of lookup tables (LUTs), slices, and flip-flops used.