Cache Memory Design for Single Bit Architecture for IoT Applications

This paper discusses single-bit architectural cache memory design. Circuit of Write Driver, six transistor static random access memory cell, latch sense amplifier, and differential sense amplifier made up the Single Bit Architecture. Aside from that, several architecture aspects such as power consumption and the number of transistors have been studied at various resistance levels. The single-bit six transistors static random-access memory cell current differential sense amplifier architecture uses 17.55μW of power and 34 transistors, resulting in the conclusion.