An Ultra-Low Power 3-T Chaotic Map based True Random Number Generator

In this paper, discrete-time chaos generator is exploited for lightweight and energy-efficient true random number generator (TRNG) implementation. The chaos generator is realized with a two-stage tent map circuit with feedback. Each stage consists of three transistors. Its transient characteristics can be tuned over a range of bias voltage to realize a family of tent map functions. The chaotic output voltage amplitude of each stage is highly sensitive to the environmental noise. The difference signal between two such chaos generators at each stage is amplified to produce a random binary output. The output of the quantized sense amplifier is sampled at twice the bit rate of each stage of tent map circuit. The proposed design was simulated using a standard 55 nm 1.2 V CMOS process. The results show that it has a very low power consumption of 10.98 μW. It has an ultra-low energy consumption of only 5.49 pJ/bit at a throughput of 2 Mbps, which is 19x lower than the recently reported state-of-the-art and the most power efficient chaotic TRNGs. The random bit stream generated by the proposed TRNG has passed entropy, ACF and NIST randomness tests.