Efficient Hardware Implementation of High-Speed Recursive Vedic Squaring Architecture on FPGA

With the ever-escalating demand for high-speed and low-power technology, the archetype of Ancient Vedic Mathematics provides a new approach to modern computing systems. Vedic Mathematics in recent years has provided an edge and garnered massive attention in real-time and high-speed modern computing systems. This work presents an efficient and optimized dedicated recursive squaring architecture designed using Urdhva Tiriyakbhyam Sutra and Karatsuba-Ofman algorithm of Ancient Vedic Mathematics and the proposed recursive squaring technique. Hardware implementation results of the proposed recursive squaring architecture for different input bit lengths (4-bit, 8-bit, 16-bit, 32-bit, and 64 bit) are presented on a Field Programmable Gate Array (FPGA) platform. The proposed squaring architecture outperforms reported state-of-the-art dedicated Vedic squaring units in terms of combinational delay and area (No. of LUTs) on an FPGA platform.