Design of a Digital Decimation Filter with High Speed and Low Complexity

Digital filter is an important component of analog-to-digital converter. The speed and complexity of digital decimation filter have a great influence on Sigma Delta analog-to-digital converter. In view of this situation, a design of high speed and low complexity digital filter is presented in this paper. A three stages cascaded architecture is adopted to reduce the number of half-band filters by increasing the downsampling rate of cascaded integrator-comb filter. The cascaded integrator-comb filter adopts a serial-parallel mixed structure to improve the speed of data processing. In order to reduce the complexity of digital filter, a novel sine compensation filter is proposed to compensate the passband attenuation and the multipliers of half-band filter are designed by time division multiplexing technique. The simulation results and analysis show that this design meets the performance requirements and its speed is increased by four times. Compared with the same type of filters, the number of multipliers, adders and registers has decreased by 45%, 31% and 26% respectively.