Design of SEU Tolerant 2D-FFT in SRAM-based FPGA

2-Dimensional fast Fourier transform (FFT) has been widely used in radar signal process. Due to the need for high performance, field programmable gate array (FPGA) is an ideal hardware device for this application. For space-borne radar platform such as synthetic aperture radar (SAR), single-event upsets (SEUs) can cause lots of soft errors in static random-access memory (SRAM) based FPGA. As to this, protecting the 2D-FFT implemented in FPGA from SEUs is very important. In this article, we analyze the critical weakness induced by SEUs in the 2D-FFT process, and then a 2D-FFT design with high SEU resilience is presented. The design utilizes the advantage of several anti-SEU methods. For butterfly control in FFT, partially triple modular redundancy (TMR) is used. For data buffers, error correction code (ECC) is applied to read and write operation. Furthermore, safe finite state machine (FSM) is adopted by important control registers. Fault injection results show that all these reinforcement technologies contribute to enhance the ability to mitigate the SEU effects.

I. Introduction

Synthetic aperture radar (SAR) has been widely used in recent years. In the traditional way of SAR imaging process flow, data sampled from the receiver are compressed in some sort of coding such as Block Adaptive Quantization (BAQ) [1] . The 8-bit data can be transformed into 3-bit or 4bit data, which decreases the whole transmission bandwidth by 50%–62.5%. But this kind of compressing method causes information loss as well. Besides, due to the limitation of downlink transmission, the time which data received on the ground has significant delay. In this tradition way of “compressing-transmission-processing”, it’s unable to realize the real-time processing [2] .