Low Power and Less Delay Circuit Shared Static Flip-Flop (LDCSSFF) for Digital Applications

A modified flip flop for high speed and low power digital applications is designed. The proposed less delay circuit shared static flip flop (LDCS
²
FF) includes five number of NOR gates and back-to-back inverters. The inverter is given with a clock signal and the following signal is given as input to the NOR gates. The proposed LDCS
²
FF is a master slave flip flop act as a storage element. The proposed LDCS
²
FF is simulated on Synopsys tool HSPICE under 32 nm BSIM4 model card for bulk CMOS technology of PTM model. The proposed LDCS
²
FF as 24 transistors with delay of 0.3 ns at 1 V applied voltage and power dissipation of
$59.6\ \mu\mathrm{W}$
at 0.8 V applied voltage.