FPGA Placement Optimization with Deep Reinforcement Learning

The Simulated annealing algorithm has been widely used in FPGA placement. In this paper, we use deep reinforcement learning to enhance the simulation annealing algorithm. We use the Deep Q-Networks based on graph convolution to implement deep reinforcement learning algorithm instead of random method to select the moving block when placer swaps blocks. Experiments show that our method can get a better placement faster than the original VTR in early stage of the placement process.