Monolithic Implementation of Chaos Modulated VCO-based Random Number Generator

This paper introduces the implementation of a monolithic random number generator. For that purpose, dual oscillator architecture with an irregular sampling of a regular signal is designed and simulated. The irregular sampling clock is generated by voltage controlled oscillator(VCO), which is modulated by a continuous-time chaotic oscillator. The proposed architecture is fully CMOS compatible and suitable for mono-lithic implementation. Therefore, it is robust against tempering attacks and external interference. It is designed in TSMC 180 nm process and requires a chip area of 0.004 mm
²
. To the best of the authors' knowledge, this work is the first monolithic implementation of chaos modulated VCO-based random number generator.