A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology

This paper presents a 20 GHz 8-bit carry-lookahead adder (CLA) using all-N-transistor (ANT) logic. By using the proposed ANT logic, an auxiliary current path through NMOS transistor is provided such that the speed limitation caused by PMOS is avoided. Besides, the FinFET device is used to improve the speed with the enhanced mobility. Moreover, the analysis of the delay time for the critical path of the 8-bit CLA is also carried out to improve the PDP (Power-Delay Product) by considering the parasitic R-C in FinFET devices. The proposed design is implemented with a typical 16 nm FinFET process. The core area is
$206.403 \times 152.506\ \mu\mathrm{m}^{2}$
. Based on post-layout simulations, the delay time is 931 ps at a 20 pF capacitive load. The simulated PDP is only 21.67 pW at 20 GHz clock rate.