Design for 3-D Stacked Neural Network Circuit with Cyclic Analog Computing

An analog-based CMOS neuron with crossbar configuration multiplier-adder circuit for three-dimensional chip stacking (3-D) cyclic signal processing deep neural network is presented. The circuit designed to verify the proposed concept is a total of four-layer stacked chips, consisting of two neuron chips that mainly perform analog multiply-accumulate (MAC) operations and two memory chips that store neuron potential (activation) and weight data. According to papers and conference presentations on accelerators for the neural network circuit, the analog MAC operation has the potential to achieve high efficiency by using the analog processing of the crossbar configuration. However, analog MAC circuit with compensation technique is required to overcome the decrease in computing accuracy due to electrical noise and element nonlinearity. In this study, we have designed and verified a highly linearity multiplier-adder circuit for highly efficient 3-D cyclic analog processing. In this paper, we focus on the current adder circuit with switched capacitor correlated double sampling (CDS) technique, to minimize non-linearity, noise, and circuit area. The proposed the analog adder circuit was designed with 180-nm and operation power supply voltage 1.8V CMOS technology, and the fabricated neuron chip that integrates 64 neurons and
$64 \times 64$
synaptic connections. As analysis results, it was confirmed that the CDS technique apply analog adder circuit reduced the noise output voltage less than 0.1mV and the range of voltage linearity was over 1.6V.