Deadbeat Current Predictive Control for PMSM Drives Based on a Single FPGA with Digital Implementation Optimization

This paper proposes a field programmable gate arrays (FPGA) digital implementation of the deadbeat current predictive control (DCPC) of permanent magnet synchronous motor (PMSM) with a sliding mode disturbance observer (SMDO). To fulfill the fast sampling and controller-integration requirements of the proposed control algorithm, a FPGA is preferred. With the flexible structure of FPGA, the motor system realizes one-step delay compensation conveniently and improves the dynamic performance as well. The designed maximized parallel pipeline architecture optimizes the computational time of the proposed current control method. The experimental in PMSM drives results that the proposed FPGA implementation achieves high performance with balanced resources consumption.