Design of Hardware Acceleration System for Video Image Reconstruction Based on AXI Bus

In view of the large amount of video image transmission and the delay of the whole frame image reconstruction after complex algorithms, this article uses FPGA platform to design a video image reconstruction hardware acceleration system based on AXI bus. The Xilinx KINTEX 7 series core board is used as the hardware platform, the onboard DDR3 is used as the video image buffer unit, and the DDR3 AXI interface is used for data transmission. Through the modular design, the frame image data buffer and the image reconstruction after complex algorithm processing are realized in the FPGA, and the conversion of Native and AXI4 protocols and the design of dynamic switching of multiple addresses are completed. At the same time, multiple ping-pong operations not only solve the problem of video image display, but also greatly reduce the time required for video caching. Finally, the video image rotation algorithm is used to verify the design of the video image reconstruction hardware acceleration system. The experimental results show that the video source with a resolution of
$1024^{\ast}768 {@} 60\text{Hz}$
can complete the real-time display after reconstruction of the video image in a short time. The data transmission rate of the system can reach 12.5Gbit/s, and the image data cache rate can reach 100Gbit/ s. The algorithm takes 13.2ms to meet the real-time performance of the system, and the display frame rate can reach 60fps.