Data-Stream Modeling of Synthesis Waveform Sequence Based on SDRAM

The waveform memory outputs the stored waveform sequence as a data stream. Ensuring the continuity of the reproduced waveforms. Synchronous dynamic random memory (SDRAM) has the advantages of large capacity and low price, and is a common solution for waveform memory. However, the SDRAM mechanism of activate-access access, burst transmission and periodic refresh makes the output waveform data stream with a certain degree of randomness, which leads to interruption of the output data stream and thus affects the continuity of the output waveform. This paper proposes a waveform sequence data-stream model of AWG to descript the transmission and breakage of the synthesis waveform sequence caused by SDRAM burst and refresh, and derive the conditions to ensure waveform sequence transmission continuity. The experiments are conducted on the FPGA+DDR3 simulation platform provided by Xilinx to verify the validity and accuracy of the synthesis waveform sequence data-stream model.