Single Event Latchup (SEL) and Single Event Upset (SEU) Evaluation of Xilinx 7nm Versal™ ACAP programmable logic (PL)

this paper examines the single-event latchup (SEL) and single event upset (SEU) response of the Xilinx 7nm XCVC1902 ES1 Versal ACAP Programmable Logic irradiated with neutrons and 64 MeV protons sources. No SEL was observed in the entire Xilinx 7nm XCVC1092 for worst case conditions. Furthermore, The SEU response for single-event upsets on configuration RAM (CRAM) cells, block RAM (BRAM) and block RAM (BRAM) cells are provided.