Delay Minimization and Evaluation in Logic Paths of RC Interconnects by Unified Logical Effort

Logical effort classical unifies the gate sizing, buffer insertion and the repeating firearm pull-out problems etc. When the interconnects are negligible then the logical effort converging to standard logical effort. While disabling the standard Logical Effort, the limitations of this method provide the timing optimization conditions in the occurrence of interconnects. The timing optimization is achieved by this way that the delay on the gate fan-in capacitance is identical to the delay due to the effective fanout resistance of the gate. The Unified Logic Effort model for the minimization and the evaluation for delay in CMOS logical gates Resistor Capacitor (RC) interconnects and with resistive wires which are included in the work. In case the interconnects are longer the principle will be the uniform size of gates and the repeaters. This method can be applied to any kind of logic paths to influence the length and size of wire and length. The analyses which are presented here on the low voltage swing and the implementation is on the CMOS 90 nm technology Generic Process Design Kit library. The simulation was done on cadence virtuoso Analog Design Environment (ADE) Electronic Design Automation (EDA) tools.