Design of Buffer Circuit for Global Interconnects Using Adiabatic Dynamic Logic

The on-chip global interconnects which are used to provide connection has become a real performance factor due to their extremely narrowed cross-section area and scaling of the device into nanometer technology. As the size of the device reduces, the global interconnect delay increases because of an increase in resistance. Due to reduction in chip size and increase in metal levels in the chip interconnect started to control the electrical characteristics thus, constituting total circuit delay. However, this delay can be reduced using the buffer insertion technique. This paper proposes the design of the Schmitt trigger circuit using the Adiabatic dynamic technique to recover energy consumption in the interconnect circuit. Authors have also simulated interconnect circuits using different buffers and a comparison is done with the proposed ADL Schmitt trigger circuit design. Simulations are carried out in a well-established 45nm/1V CMOS process. It is observed that the overall power for interconnect circuit with the proposed ADL Schmitt trigger as a buffer is 3.20pW which is better in comparison with other circuits.