Design and Implementation of Area-Power Efficient Generic Modular Adder using Flagged Prefix Addition Approach

Modular adders are employed in the implementation of multipliers, reverse converters, digital signal processors, cryptography and other various residue number system applications. This paper proposes novel adder architecture for moduli of the form 2
ⁿ
-K where K is any integer in the range of 3 ≤ K ≤ 2
ⁿ
-1. The Proposed architecture uses Sklansky parallel prefix adder (PPA) in the first stage adder along with the flagged prefix addition technique in the second stage. Use of flagged prefix addition approach significantly reduces the area and power dissipation when compared with published work. Synthesis is done using 90 nm SAED generic library on Synopsys Design Compiler tool and VHDL is used to model the structures under investigation over an input bit range of 7 ≤ n ≤ 15. Reduction up to 42.5% is obtained in the area-power product of the proposed modular adder structure when compared to earlier presented work.