High Throughput Folded Architecture of AES

Advanced Encryption Standard (AES) is the most widely used crypto algorithms in various secured data commu-nications such as SSL, and so on. This paper proposes a high throughput folded architecture to perform 128-bit AES encryption/decryption, where four AES operations can be performed in parallel. The hardware utilization and throughput of this proposed folded AES design is lying in between the conventional folded and parallel designs. All the existing and proposed AES designs are implemented with Virtex-6 FPGA (XC6VLX760) using Xilinx. The synthesis results show that our proposed design achieves 84.65% of improvement in the throughput than the existing folded design with looping parameter-2 (Fig. 4 of [7]).