Spin-on-carbon Material Buried Voids Defect Analysis And Improvement In Via Patterning Process With Double Exposure Lithography

Double patterning lithography for contact hole patterning is a necessary approach for the manufacturing of semiconductor devices at the 40 nm half pitch node and below, because sub-50nm size contact hole with 193nm ArF immersion single exposure has various challenges such as narrow process window, large mask error enhancement factor (MEEF), poor circularity, and low image contrast compared to line & space patterning. And spin-on-carbon (SOC) hard mask under layer material deposition has become inevitable process to achieve better planarization and gap fill properties and smaller contact hole pattering. However low defect count is main requirement for the under layer material for tri-layer patterning. Recently, we found especial hole-pattern defect on spin-on-carbon material applied to double exposure lithography for advanced node. This defect is like abnormity hole-pattern with about 50-200nm diameter, and it is difference with familiar bubble defect which contained inside spin-applied films as coated. Especially the second patterning process only suffer this defect. In this paper, we will analysis the defect fail model and introduce the experimental results of hole-type defect forming process for contact hole patterning. We also presented data show the optimized setting of SOC coater parameters can suppress the defect level by >90% comparing to the original standard recipe, such as dispense condition, DIW rinse and pre_treatment before coat.