A Study of Overlay Accuracy Improvement on Process Induced Asymmetry Effect

With the development of advanced technology nodes, the specifications for overlay has become more tightened. Furthermore, the critical dimension of the device structure becomes smaller and the overlay mark formed based on the design rule following the device structure can be more impacted by process variation. In this paper, the asymmetry of the overlay mark formed by the fin structure was investigated, and the phenomenon of the center of symmetry of overlay mark changing across wafer was found. The effect of an asymmetric target profile on overlay performance was simulated by KLA's Metrology Target Design (MTD) software. It was found that the OVL accuracy could be influenced by the asymmetry of metrology target. However, the overlay error induced by the target asymmetry profile could be characterized and reduced by using a particular wavelength combined with suitable optical polarization setting on the overlay tool. We conclude that virtual metrology technology is helpful for overlay metrology recipe optimization by understanding and alleviating the influence of metrology target asymmetry which can also reduce the development cycle time and wafer cost as well.