Risc-V Random Test Generator

The RISC-V compliance test-suites are a set of directed testcases, they are used to verify RISC-V processor meets all the requirements under RISC-V Instruction Set Architecture (RISC-V ISA) specification or not. For processor design, there are many micro-architectures, so the compliance test-suites only ensure that the function of the processor meets ISA, but not bug free design. Additional, to verify a function of a processor, needing a large amount of dedicated testcases with certain coverage to highly confirm this function meets implementation specification. In this paper, we propose a RISC-V Random Test Generator (RISC-V RTG) is used to generate dedicated testcases with custom coverage to verify a processor based on integer instructions of RISC-V ISA. Our RISC-V RTG doesn’t replace the compliance test-suites, but it helps improve the quality of verification tasks for many micro-architectures in processor design.