Comparative Analysis and Optimization of the SystemC-AMS Analog Simulation Efficiency of Resistive Crossbar Arrays

When structured as a crossbar array, non-volatile resistive memories form the core of emerging analog accelerators for heterogeneous computing systems. Because of its underlying C++ modelling platform, SystemC-AMS holds promise of a unifying tool to correlate the electrical properties of such devices directly to the quality metrics of the application. Unfortunately, the support for electrical modeling of resistive crossbar arrays in SystemC-AMS is currently still in its infancy. Similarly, its analog simulation efficiency for these devices has never been characterized in detail. This paper aims at a comparative analysis of SystemC-AMS versus mainstream analog simulation engines when running the fundamental circuit simulation types of a resistive crossbar array. In order to make simulation speed competitive and scalable, subtle inefficiencies are identified and optimized, to the extent that SystemC-AMS exhibits an area of specialty in Monte Carlo analysis, with up to 93% lower simulation time than a commercial circuit simulator. As a realistic case study, we focus on an array of oxide-based resistive switching memories (RRAMs), using device models that span different trade-offs between compute workload and simulation speed.