Design of a Ring-Amplifier Robust Against PVT Variations in Deep-Nanoscale FinFET CMOS

This paper describes the design and the electrical simulation results, at device level, of a proposed ring-amplifier (RINGAMP) for industrial applications. The proposed topology has been fairly compared with other topologies presented in literature, showing better static (open-loop DC gain with less variability), dynamic performance (both, SNR and THD) and robustness against PVT corners and presenting a faster response. The simulated key performance parameters demonstrate to be compatible with the required specifications for a residue amplifier to be readily employed in the context of a 10-bit high-speed two-stage pipeline ADC.