All-Digital VCO-ADC TAD Using 4CKES-Type in 16-nm FinFET CMOS for Technology Scaling With Stochastic-ADC Method

This paper presents a fast and very-scalable ADC architecture with a 4-clock-edge-shift (4CKES) type of an all-digital VCO-based-ADC Time-A/D converter (TAD). 4CKES-type TAD (4CKES-TAD) uses an inverter-based ring-delay-line (RDL) shared with four logic-modules, which consist of latches, encoders and subtractors with a newly developed FinFET-based clock buffer. TAD total performance is simply improved with more advanced technologies, confirmed in a 16-nm FinFET CMOS compared to 40-nm 4CKES-TAD. Using post-layout simulation, the differential-setup with four 4CKES-TADs produces 10-GS/s, 6.9-bit resolution, 3.5-ENOB with 0.0077 mm
²
without any calibration or interleaved method. According to the roadmap of technology-scaling, TAD-arrays as a stochastic-ADC in much finer processes can be realized as a very fast ADC for high-speed serial links and RF-digitization of more advanced mixed-signal SoCs/ASICs.