Delay-lines jitter modeling and efficiency analysis in FinFET technology

In this paper we devised a simple analytical jitter model for the shunt capacitor delay line and the current starved delay line. In the model we also considered the layout resistances and capacitances effects, the flicker noise, and the gate resistances noise which are not negligible in FinFET technology. Then, we verified the model validity through the design of prototypes in 5nm technology, obtaining a good match between the simulation and the model with a 15% maximum error. Lastly, we compared the efficiency of the circuits, and we analyze the effects of the capacitive load tuning range on the capacitive load delay line efficiency, showing how critical this is in the design and choice of the delay line topology.