Human- and Machine-Readable Requirements Formulation for Lab Verification Automation

The increasing complexity of modern smart power devices leads to a rise of functional requirements. To improve the productivity within the lab verification flow, requirements may be formalized with property specification language (PSL). Currently the formalization is executed manually, which is time consuming, scales badly for complex circuits and is prone to errors. Therefore, an approach is needed that enables a quick formalization and subsequent automated verification of requirements. The proposed methodology allows to formalize functional requirements in human and machine-readable fashion, based on a SysML behavioural description. It provides semi-formalization instead of formalization, which makes the description more human readable and easier to debug. Complex stimuli are automatically generated to traverse through the state machine into a target state, to check if a specific requirement, asserted onto the measurements, is satisfied. In a case study of a mid-complexity smart power device, 94% of the total requirements are formalized and are automatically verified in the lab. This leads to a drastic reduction in verification time.