Chiplet-based Architecture Design for Multi-Core Neuromorphic Processor

Nowadays, artificial neural networks have become a significant part to solve real-world problems. As neural networks algorithms keep on growing in complexity and dimension, large operational resources and data storage are required for enabling rapid inference. This leads to a trend in developing high throughput and energy efficient neural network hardware accelerators. However, as the technology nodes continue to scale down, the total fabrication costs and design challenges associated with large-scale neural network hardware accelerators keep on growing as well. Additionally, the total development time is increased due to design complexity and fabrication yield issues. In this paper, a chiplet-based architecture for a multi-core neuromorphic processor is proposed. This design is developed with a chip-package co-design flow. It provides a fundamental base architecture that can be reusable for a variety of neuromorphic computing applications by just scaling the number of chip in a package. Compared with large-scale conventional SoC designs, the proposed chiplet-based designs have lower fabrication cost due to better yield of small chiplets. Also, existing IPs from different technology nodes are reused with 2.5D integration technology.