A 30-to-70-GHz CMOS Amplifier for 300-GHz Heterodyne Receivers

A method is presented for designing a wideband multistage amplifier that does away with the iterative design tweaking necessitated by interstage loading. A known but rarely adopted approach to prevent loading is to match each stage to certain real source and load impedances and then cascade all stages. But following matching-network reduction and tuning are required anyway. The proposed method proceeds by first making each stage as unilateral as possible (as usual) and then designing an associated interstage network in such a way that no post-cascade tuning is necessary. The decibel-gain of a multistage amplifier thus designed is shown to be given simply by the sum of the decibel-gains of the constituent stages. A 30-to-70-GHz CMOS IF amplifier prototype designed in this way is presented, showing good agreement between simulation and measurement.